JPH0435779B2 - - Google Patents
Info
- Publication number
- JPH0435779B2 JPH0435779B2 JP62024223A JP2422387A JPH0435779B2 JP H0435779 B2 JPH0435779 B2 JP H0435779B2 JP 62024223 A JP62024223 A JP 62024223A JP 2422387 A JP2422387 A JP 2422387A JP H0435779 B2 JPH0435779 B2 JP H0435779B2
- Authority
- JP
- Japan
- Prior art keywords
- central processing
- processing unit
- signal
- input
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Advance Control (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62024223A JPS63282528A (ja) | 1987-02-04 | 1987-02-04 | 中央処理装置実行命令の検出方式 |
DE19883852660 DE3852660T2 (de) | 1987-02-04 | 1988-02-02 | Befehlsablauferkennungssystem und -methode für zentrale Verarbeitungseinheit. |
EP19880101433 EP0280890B1 (en) | 1987-02-04 | 1988-02-02 | System and method for detecting the execution of an instruction in a central processing unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62024223A JPS63282528A (ja) | 1987-02-04 | 1987-02-04 | 中央処理装置実行命令の検出方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63282528A JPS63282528A (ja) | 1988-11-18 |
JPH0435779B2 true JPH0435779B2 (en]) | 1992-06-12 |
Family
ID=12132275
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62024223A Granted JPS63282528A (ja) | 1987-02-04 | 1987-02-04 | 中央処理装置実行命令の検出方式 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0280890B1 (en]) |
JP (1) | JPS63282528A (en]) |
DE (1) | DE3852660T2 (en]) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5075840A (en) * | 1989-01-13 | 1991-12-24 | International Business Machines Corporation | Tightly coupled multiprocessor instruction synchronization |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58197553A (ja) * | 1982-05-12 | 1983-11-17 | Mitsubishi Electric Corp | プログラム監視装置 |
US4727480A (en) * | 1984-07-09 | 1988-02-23 | Wang Laboratories, Inc. | Emulation of a data processing system |
US4791557A (en) * | 1985-07-31 | 1988-12-13 | Wang Laboratories, Inc. | Apparatus and method for monitoring and controlling the prefetching of instructions by an information processing system |
-
1987
- 1987-02-04 JP JP62024223A patent/JPS63282528A/ja active Granted
-
1988
- 1988-02-02 EP EP19880101433 patent/EP0280890B1/en not_active Expired - Lifetime
- 1988-02-02 DE DE19883852660 patent/DE3852660T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE3852660D1 (de) | 1995-02-16 |
EP0280890A3 (en) | 1990-08-22 |
EP0280890B1 (en) | 1995-01-04 |
JPS63282528A (ja) | 1988-11-18 |
DE3852660T2 (de) | 1995-05-11 |
EP0280890A2 (en) | 1988-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5430862A (en) | Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution | |
US4942519A (en) | Coprocessor having a slave processor capable of checking address mapping | |
US4635193A (en) | Data processor having selective breakpoint capability with minimal overhead | |
KR19980069757A (ko) | 마이크로프로세서 및 멀티프로세서 시스템 | |
US4747045A (en) | Information processing apparatus having an instruction prefetch circuit | |
JPS61204758A (ja) | コ・プロセツサ制御方式 | |
JPS645330B2 (en]) | ||
JPH07120338B2 (ja) | 共同プロセッサによる命令の実行をデータプロセッサが調整する方法および該データプロセッサ | |
JPH0435779B2 (en]) | ||
JPS62197831A (ja) | デ−タ処理装置 | |
JP2619425B2 (ja) | シーケンスコントローラ | |
JP2808757B2 (ja) | デバッグ用マイクロプロセッサ | |
JP2859048B2 (ja) | マイクロコンピュータ | |
JPH06324861A (ja) | Cpu制御システム及び制御方法 | |
JPH0241770B2 (en]) | ||
EP0138045A2 (en) | Apparatus and method for synchronization of peripheral devices via bus cycle alteration in a microprocessor implemented data processing system | |
JP2883335B2 (ja) | 情報処理装置 | |
JPH0259829A (ja) | マイクロコンピュータ | |
JPH07121396A (ja) | エミュレータ | |
JP2644104B2 (ja) | マイクロプロセッサ | |
JPS595932B2 (ja) | デ−タ処理方式 | |
JPH04290130A (ja) | プロセッサのエラー管理方式 | |
JP2022015197A (ja) | デバッグ用インサーキットエミュレータ装置 | |
JPH0752402B2 (ja) | データ処理装置 | |
JPS6221130B2 (en]) |